AD6121ARS 3V CDMA (QPSK) приемник ПЧ с интегрированным регулятором напряжения

http://datasheet.elcodis.com/pdf2/72/98/729842/ad6121ars.pdf

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FEATURES

Fully Compliant with IS98A and PCS Specifications

CDMA, W-CDMA, AMPS, and TACS Operation

Linear IF Amplifier

5.9 dB Noise Figure

–47.5 dB to +47 dB Linear-in-dB Gain Control

Quadrature Demodulator

Demodulates IFs from 50 MHz to 350 MHz

Integral Low Dropout Regulator

200 mV Voltage Drop

Accepts 2.9 V to 4.2 V Input from Battery

Low Power

10 mA at Midgain

<1
A Sleep Mode Operation

Companion Transmitter IF Chip Available (AD6122)

APPLICATIONS

CDMA, W-CDMA, AMPS, and TACS Operation

QPSK Receivers

GENERAL DESCRIPTION

The AD6121 is a low power receiver IF subsystem specifically designed for CDMA applications. It consists of high dynamic range IF amplifiers with voltage controlled gain, a divide-by-two quadrature generator, an I and Q demodulator, and a power￾down control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V.

The gain control input accepts an external gain control voltage input from a DAC. It provides 94.5 dB of gain control with a nominal 52.5 dB/V scale factor when using an internal voltage reference. The gain control interface reference input can be connected to either the internal reference or an external reference.

The I and Q demodulator provides differential quadrature base￾band outputs to interface with CDMA baseband converters. A divide-by-two quadrature generator followed by dual polyphase filters ensures maximum ±2.5° quadrature accuracy.

The AD6121 IF Subsystem is fabricated using a 25 GHz ft BiCMOS silicon process and is packaged in a 28-lead SSOPa nd a 32-leadless LPCC chip scale package (5 mm × 5 mm).